drm/amd/display: Raise DPG height during timing synchronization

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[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.

[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.

Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Taimur Hassan 2020-10-04 15:20:45 -04:00 • committed by Alex Deucher

parent 1db522cd03

commit a47cc3ab05

5 changed files with 41 additions and 1 deletions

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20

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

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1

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c

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12

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c

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4

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h

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5

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

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