riscv: abstract out CSR names for supervisor vs machine mode

Many of the privileged CSRs exist in a supervisor and machine version that are used very similarly. Provide versions of the CSR names and fields that map to either the S-mode or M-mode variant depending on a new CONFIG_RISCV_M_MODE kconfig symbol. Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com> and Paul Walmsley <paul.walmsley@sifive.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> # for drivers/clocksource, drivers/irqchip [paul.walmsley@sifive.com: updated to apply] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2026-10-09 18:15:49 +00:00 · 2019-10-28 13:10:32 +01:00 · 2019-10-28 13:10:32 +01:00 · a4c3733d32
commit a4c3733d32
parent 0c3ac28931
21 changed files with 199 additions and 135 deletions
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
--- a/arch/riscv/include/asm/irqflags.h
+++ b/arch/riscv/include/asm/irqflags.h
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
--- a/arch/riscv/include/asm/ptrace.h
+++ b/arch/riscv/include/asm/ptrace.h
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
--- a/arch/riscv/kernel/fpu.S
+++ b/arch/riscv/kernel/fpu.S
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
--- a/arch/riscv/kernel/perf_callchain.c
+++ b/arch/riscv/kernel/perf_callchain.c
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
--- a/arch/riscv/lib/uaccess.S
+++ b/arch/riscv/lib/uaccess.S
--- a/arch/riscv/mm/extable.c
+++ b/arch/riscv/mm/extable.c
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c