ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support

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The existing code assumes a 19.2 MHz MCLK as the default
hardware configuration. This is valid for CherryTrail but
not for Baytrail.

Add explicit MCLK configuration to set the 19.2 clock on/off
depending on DAPM events.

This is a prerequisite step to enable devices with Baytrail
and RT5645 such as Asus X205TA

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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Pierre-Louis Bossart 2017-01-26 14:09:38 -06:00 • committed by Mark Brown

parent 39d7548568

commit a50477e55f

1 changed files with 71 additions and 13 deletions

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sound/soc/intel/boards/cht_bsw_rt5645.c

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