KVM: PPC: Book3S PR: Emulate TIR register

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In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.

Signed-off-by: Alexander Graf <agraf@suse.de>

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Alexander Graf 2014-04-25 16:07:21 +02:00

parent f8f6eb0d18

commit a5948fa092

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arch/powerpc/kvm/book3s_emulate.c

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