dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints

Browse source

Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".

Add missing top-level constraints for clock-names and reset-names.

Link: https://lore.kernel.org/linux-pci/20240818172843.121787-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

...

This commit is contained in:

Krzysztof Kozlowski 2024-08-18 19:28:43 +02:00 • committed by Krzysztof Wilczyński

parent c62a0b8fe8

commit a5c1bf7e9a

No known key found for this signature in database

GPG key ID: 7C64768D3DE334E7

1 changed files with 6 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

8

Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml

View file