clk: renesas: Updates for v5.17 (take two)

- Add support for the new R-Car S4-8 (R8A779F0) SoC,
   - Add GPU clock and resets on RZ/G2L,
   - Miscellaneous fixes and improvements.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYbxjuwAKCRCKwlD9ZEnx
 cPqVAP9nga20zmYmTzwf6/KINu2Nk2GyUeOoYfmZgJBb1579yAEAinDtjFcVisfq
 EVOJvY9WjZDzV1oYehMl2aI2OCN3VgQ=
 =SDQ2
 -----END PGP SIGNATURE-----

Merge tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
 - Add GPU clock and resets on Renesas RZ/G2L
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a07g044: Add GPU clock and reset entries
  clk: renesas: r9a07g044: Add mux and divider for G clock
  clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
  clk: renesas: cpg-mssr: Add support for R-Car S4-8
  clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
  dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
  dt-bindings: power: Add r8a779f0 SYSC power domain definitions
This commit is contained in:
Stephen Boyd 2021-12-28 21:42:12 -08:00
commit a5ce1d5118
12 changed files with 748 additions and 343 deletions