parisc: disable preemption during local tlb flush

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flush_cache_mm() and flush_cache_range() fetch %sr3 via mfsp().
If it matches mm->context, they flush caches and the TLB. However,
the TLB is cpu-local, so if the code gets preempted shortly after
the mfsp(), and later resumed on another CPU, the wrong TLB is flushed.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>

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Sven Schnelle 2021-10-09 20:24:35 +02:00 • committed by Helge Deller

parent ec5c115050

commit a5e8ca3783

1 changed files with 6 additions and 0 deletions

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arch/parisc/kernel/cache.c

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