drm/i915: merge VLV eDP and DP AUX clock divider calculation

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On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we
can calculate for both the clock divider for the 2MHz target rate at the
same place. Afterwards we can also replace the is_cpu_edp() check with a
check for port A.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Imre Deak 2013-05-16 14:40:35 +03:00 • committed by Daniel Vetter

parent 982a38667d

commit a62d0834de

1 changed files with 3 additions and 3 deletions

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drivers/gpu/drm/i915/intel_dp.c

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