clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks

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HSI1/2 PCIe and HSI0 USBDP debug outputs are fixed divide-by-8.
OTP also uses 1/8 from oscclk. Replace incorrect div clocks with
fixed-factor clocks to reflect hardware.

Fixes: bdd03ebf72 ("clk: samsung: Introduce Exynos990 clock controller driver")
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-3-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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Denzeel Oliva 2025-08-30 16:28:40 +00:00 • committed by Krzysztof Kozlowski

parent ce2eb09b43

commit a66dabcd2c

1 changed files with 12 additions and 7 deletions

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drivers/clk/samsung/clk-exynos990.c

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