drm/i915: Read C0DRB3/C1DRB3 as 16 bits again

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commit 04d019961f upstream.

We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them
as such.

Fixes: 1c8242c3a4 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-3-ville.syrjala@linux.intel.com
(cherry picked from commit f765a5b48c)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Ville Syrjälä 2021-04-21 18:33:59 +03:00 • committed by Greg Kroah-Hartman

parent 17928443db

commit a67c80dcb4

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

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