net/mlx5: HWS, Fix pool size optimization

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The optimization to create a size-one STE range for the unused direction
was broken. The hardware prevents us from creating RTCs over unallocated
STE space, so the only reason this has worked so far is because the
optimization was never used.

Signed-off-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Link: https://patch.msgid.link/1744312662-356571-8-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

...

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Vlad Dogaru 2025-04-10 22:17:37 +03:00 • committed by Jakub Kicinski

parent 0456269476

commit a68334f975

1 changed files with 2 additions and 2 deletions

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drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c

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