drm/i915/adlp+: Allow DC states along with PW2 only for PWB functionality

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A recent bspec update added a restriction on when DC states can be enabled:

[Before enabling DC states:]

"""
PG2 can be kept enabled only because PGB requires PG2.
Do not use PG2 functions, such as type-C DDIs.

DMC will dynamically control PG1, PGA, PG2, PGB.
"""

Accordingly prevent DC states if PW2 (aka PG2) is enabled for any other
functionality.

Bpsec: 49193

Fixes: 88c4879384 ("drm/i915: Use separate "DC off" power well for ADL-P and DG2")
Reported-by: Kai Vehmanen <kai.vehmanen@intel.com>
Tested-by: Ambica Pramod <ambica.pramod@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606172822.1891897-1-imre.deak@intel.com
(cherry picked from commit f4e498eb12)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

...

This commit is contained in:

Imre Deak 2023-06-06 20:28:22 +03:00 • committed by Tvrtko Ursulin

parent 274d4b96b1

commit a6b4229d85

1 changed files with 8 additions and 8 deletions

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drivers/gpu/drm/i915/display/intel_display_power_map.c

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