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arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins

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The HW user manual for the Renesas RZ/T2H and the RZ/N2H states that for
SDR104, SDR50, and HS200 to work properly the eMMC/SDHI interface pins
have to be configured as specified below:
  - SDn_CLK pin - drive strength: Ultra High, slew rate: Fast,
  - Other SDn_* pins: drive strength: High, slew rate: Fast,
    Schmitt trigger: disabled (not applicable to SDn_RST pins).

HS DDR and DDR50 are currently not supported, and for every other bus
mode the eMMC/SDHI interface pins should be configured as specified
below:
  - SDn_CLK pin - drive strength: High, slew rate: Fast,
  - Other SDn_* pins: drive strength: Middle, slew rate: Fast,
    Schmitt trigger: disabled (not applicable to SDn_RST pins).

Adjust the pin definitions accordingly.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20260514210220.7616-1-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Fabrizio Castro 2026-05-14 22:02:17 +01:00 • committed by Geert Uytterhoeven
commit a6c4c7114b
1 changed files with 136 additions and 11 deletions
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