drm/i915: Configure GAM_ECOCHK appropriatly for Gen7

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IVB and HSW use different encodings for the PPGTT cacheability bits in
the GAM_ECOCHK register.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2013-04-04 15:13:42 +03:00 • committed by Daniel Vetter

parent a65c2fcd00

commit a6f429a5a2

2 changed files with 14 additions and 2 deletions

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11

drivers/gpu/drm/i915/i915_gem_gtt.c

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5

drivers/gpu/drm/i915/i915_reg.h

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