drm/amd/display: correct register Clock Gater incorrectly disabled

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[why]
The "dpp35_dppclk_control" routine is incorrectly disabling the register clock gater
when the DPP is enabled.

The "DISPCLK_R_GATE_DISABLE" should never be set to 1 in the normal operating mode.
This will disable the clock gater and the DPPCLK register clock branch will always be running.
As a consequence, the dynamic power will be higher than expected.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Charlene Liu 2024-09-11 20:35:39 -04:00 • committed by Alex Deucher

parent 1c6b16ebf5

commit a6f59c0445

1 changed files with 4 additions and 6 deletions

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drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

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