drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip

Browse source

Xe3 is capable of switching automatically to min ddb allocation
(not using any extra blocks) or interim SAGV-adjusted allocation
in case if async flip is used. Introduce the minimum and interim
ddb allocation configuration for that purpose. Also i915 is
replaced with intel_display within the patch's context

v2: update min/interim ddb declarations and handling (Ville)
    update to register definitions styling
    consolidation of minimal wm0 check with min DDB check

Bspec: 69880, 72053
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-4-vinod.govindapillai@intel.com

...

This commit is contained in:

Stanislav Lisovskiy 2024-11-21 13:27:26 +02:00 • committed by Vinod Govindapillai

parent aac49b862a

commit a831920c37

4 changed files with 118 additions and 18 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

8

drivers/gpu/drm/i915/display/intel_display_types.h

View file

26

drivers/gpu/drm/i915/display/skl_universal_plane.c

View file

15

drivers/gpu/drm/i915/display/skl_universal_plane_regs.h

View file

87

drivers/gpu/drm/i915/display/skl_watermark.c

View file