diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index d28d69162427..512de3597581 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -453,15 +453,17 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -472,15 +474,17 @@ &pcie3a { num-lanes = <2>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -489,15 +493,17 @@ }; &pcie3b { - perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3b_default>; status = "okay"; }; +&pcie3b_port0 { + reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; +}; + &pcie3b_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -506,15 +512,17 @@ }; &pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie4_default>; status = "okay"; }; +&pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +}; + &pcie4_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 44177e9b64b5..83d5f1d9e79b 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -366,15 +366,17 @@ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "disabled"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -387,15 +389,17 @@ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index dcdeefd28728..67f0576f2824 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -628,9 +628,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -646,10 +643,12 @@ status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; +&pcie3a { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -665,12 +664,14 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -687,6 +688,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index f3c00be67081..aa408f435b28 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -739,9 +739,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -757,12 +754,14 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -772,6 +771,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index abd9c5a67b9f..7b21eca62908 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -933,9 +933,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -951,10 +948,12 @@ status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; +&pcie3a { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -970,12 +969,14 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -985,6 +986,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index f2b4470d4407..3d589f05b90e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -486,9 +486,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -504,10 +501,12 @@ status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; +&pcie3a { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie3a_default>; @@ -523,12 +522,14 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -538,6 +539,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 47282e3ba866..9da2ffb318d0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -624,9 +624,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -642,12 +639,14 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -657,6 +656,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a2bd6b10e475..1c2bb7b07d93 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2220,9 +2220,6 @@ power-domains = <&gcc PCIE_4_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie4_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie4_port0: pcie@0 { @@ -2230,6 +2227,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie4_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2331,9 +2330,6 @@ power-domains = <&gcc PCIE_3B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3b_port0: pcie@0 { @@ -2341,6 +2337,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3b_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2442,9 +2440,6 @@ power-domains = <&gcc PCIE_3A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3a_port0: pcie@0 { @@ -2452,6 +2447,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3a_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2556,9 +2553,6 @@ power-domains = <&gcc PCIE_2B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2b_port0: pcie@0 { @@ -2566,6 +2560,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie2b_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2667,9 +2663,6 @@ power-domains = <&gcc PCIE_2A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2a_port0: pcie@0 { @@ -2677,6 +2670,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie2a_phy>; + #address-cells = <3>; #size-cells = <2>; ranges;