drm/i915: Query the vswing levels per-lane for tgl dkl phy

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Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Note that the code only does two loops, with each one writing the
levels for two TX lanes. The register offsets also look a bit funny
because each time through the loop we write to the exact same
register offsets. The crucial bit is the HIP_INDEX_REG
write that steers the same mmio window into different places.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-11-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

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This commit is contained in:

Ville Syrjälä 2021-10-06 23:49:31 +03:00

parent 305448e557

commit a905ced613

1 changed files with 19 additions and 14 deletions

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drivers/gpu/drm/i915/display/intel_ddi.c

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