drm/i915: MIPI Timings related changes for dual link

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hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Gaurav K Singh 2014-12-04 10:58:54 +05:30 • committed by Daniel Vetter

parent 3770f0eec4

commit aa102d286a

1 changed files with 24 additions and 13 deletions

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drivers/gpu/drm/i915/intel_dsi.c

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