From 87c83a27b80062d0ca5dca408b7a7db42027a582 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 16 Sep 2025 16:02:43 +0100 Subject: [PATCH 01/41] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes Add USB3 PHY/Host nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250916150255.4231-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 7a469de3bb62..d1bf16c6ff6b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -853,6 +853,36 @@ interrupts = ; }; + xhci: usb@15850000 { + compatible = "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy: usb-phy@15870000 { + compatible = "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; From 6ea91acf0f67a7e6dd1e899955346e00778d7b0f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 16 Sep 2025 16:02:44 +0100 Subject: [PATCH 02/41] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST Enable USB3.2 Gen2 Host controller(a.k.a USB3HOST) on the RZ/G3E SMARC EVK platform. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250916150255.4231-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 10 ++++++++++ arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 08e814c03fa8..0fd90d79b020 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -164,6 +164,11 @@ ; /* SD1DAT3 */ }; }; + + usb3_pins: usb3 { + pinmux = , /* USB30_VBUSEN */ + ; /* USB30_OVRCURN */ + }; }; &scif0 { @@ -179,3 +184,8 @@ vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sd1_pvdd>; }; + +&xhci { + pinctrl-0 = <&usb3_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index 58561da3007a..8b3765b8267d 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -106,3 +106,11 @@ status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; From 00d3dbc4744dc3213c150fb33c47697a7c60fb2f Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 22 Oct 2025 10:31:40 +0300 Subject: [PATCH 03/41] arm64: dts: renesas: rzt2h-n2h-evk: Add note about SD1 1.8V modes 1.8V operation of SD1 requires the jumper to be placed on the correct pins of a connector on these Evaluation Kits. 1.8V is needed to achieve the higher rated speeds like SDR104. Add a note about it to make sure no one else spends too much time figuring this out. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251022073141.1989762-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts | 3 +++ arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index b7706d0bc3aa..d1474f1bd523 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -26,6 +26,9 @@ * P17_4 = SD1_CD; SW2[3] = ON * P08_5 = SD1_PWEN; SW2[3] = ON * P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON + * To enable proper operation in 1.8V modes, CN77 must have pins 2 and 3 + * connected by the jumper. This connects SD1 power-supply control IC output + * back to VCC1833_7. */ #define SD1_MICRO_SD 1 diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 17c0c79fbd96..eaf73868783b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -30,6 +30,9 @@ /* * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON * P08_6 = SD1_IOVS; DSW5[3] = ON + * To enable proper operation in 1.8V modes, JP21 must have pins 2 and 3 + * connected by the jumper. This connects SD1 power-supply control IC output + * back to VCC1833_7. */ #define SD1_MICRO_SD 1 From 0154078db6abbc8f1adc216e1b20472f0b50aaf8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Oct 2025 22:23:12 +0100 Subject: [PATCH 04/41] arm64: dts: renesas: r9a09g057: Add FCPV and VSPD nodes Add FCPV and VSPD nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251023212314.679303-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 4df32d7e9998..59dc6025749b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1348,6 +1348,30 @@ }; }; }; + + fcpvd: fcp@16470000 { + compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + }; + + vspd: vsp@16480000 { + compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x16480000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,fcp = <&fcpvd>; + }; }; stmmac_axi_setup: stmmac-axi-config { From ebb6adecb992d5c6f16a830b9361092a1e791755 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Oct 2025 22:23:13 +0100 Subject: [PATCH 05/41] arm64: dts: renesas: r9a09g057: Add DU and DSI nodes Add DU and DSI nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251023212314.679303-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 59dc6025749b..c09578d2c962 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1349,6 +1349,71 @@ }; }; + dsi: dsi@16430000 { + compatible = "renesas,r9a09g057-mipi-dsi"; + reg = <0 0x16430000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, + <&cpg CPG_MOD 0xeb>; + clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg 0xd8>, <&cpg 0xd7>; + reset-names = "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; + }; + + du: display@16460000 { + compatible = "renesas,r9a09g057-du"; + reg = <0 0x16460000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + fcpvd: fcp@16470000 { compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv"; reg = <0 0x16470000 0 0x10000>; From 947acdadcae0b1759f082266893d277cfb5b29c1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Oct 2025 22:23:14 +0100 Subject: [PATCH 06/41] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable DU and DSI Enable DU, DSI and adv7535 HDMI encoder on RZ/V2H Evaluation Kit. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251023212314.679303-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 445fce156f73..90d93116fabd 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -35,6 +35,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + keys: keys { compatible = "gpio-keys"; @@ -103,12 +114,36 @@ #clock-cells = <0>; clock-frequency = <32768>; }; + + /* 12MHz crystal for ADV7535 */ + y1: y1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -174,6 +209,42 @@ clock-frequency = <400000>; status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + interrupt-parent = <&pinctrl>; + interrupts = ; + clocks = <&y1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &i2c6 { From 71270e792c72da7c0078a0af67f7f15aa24c1403 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sat, 1 Nov 2025 16:29:51 +0900 Subject: [PATCH 07/41] arm64: dts: renesas: r9a09g057h48-kakip: Enable SPI NOR Flash This enables W25Q256JWPIM NOR Flash connected to XSPI. Additionally, this adds fixed 1.8V regulator node (`reg_1p8v`) required for NOR Flash. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251101072951.2681630-1-iwamatsu@nigauri.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g057h48-kakip.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index adf3ab8aef2b..e8523bb6705a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -30,6 +30,15 @@ reg = <0x0 0x48000000 0x1 0xF8000000>; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; @@ -112,6 +121,18 @@ pinmux = ; /* SD0_CD */ }; }; + + xspi_pins: xspi0 { + ctrl { + pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; + output-enable; + }; + + io { + pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3"; + renesas,output-impedance = <3>; + }; + }; }; &qextal_clk { @@ -134,3 +155,21 @@ status = "okay"; }; + +&xspi { + pinctrl-0 = <&xspi_pins>; + pinctrl-names = "default"; + assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>; + assigned-clock-rates = <133333334>; + status = "okay"; + + flash@0 { + /* W25Q256JWPIM */ + compatible = "jedec,spi-nor"; + reg = <0>; + vcc-supply = <®_1p8v>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; From 6569dced2b98fc44c55640efc735d301eeac2387 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 3 Nov 2025 20:03:47 +0000 Subject: [PATCH 08/41] arm64: dts: renesas: r9a09g056: Add FCPV and VSPD nodes Add FCPV and VSPD nodes to RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251103200349.62087-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 8781c2fa7313..dd0908e8c156 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -955,6 +955,30 @@ }; }; }; + + fcpvd: fcp@16470000 { + compatible = "renesas,r9a09g056-fcpvd", "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + }; + + vspd: vsp@16480000 { + compatible = "renesas,r9a09g056-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x16480000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,fcp = <&fcpvd>; + }; }; stmmac_axi_setup: stmmac-axi-config { From d8332e5f3384c17b55025cfcf35733eeffeac3c5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 3 Nov 2025 20:03:48 +0000 Subject: [PATCH 09/41] arm64: dts: renesas: r9a09g056: Add DU and DSI nodes Add DU and DSI nodes to RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251103200349.62087-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index dd0908e8c156..c276cdc730bd 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -956,6 +956,71 @@ }; }; + dsi: dsi@16430000 { + compatible = "renesas,r9a09g056-mipi-dsi", "renesas,r9a09g057-mipi-dsi"; + reg = <0 0x16430000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, + <&cpg CPG_MOD 0xeb>; + clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg 0xd8>, <&cpg 0xd7>; + reset-names = "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; + }; + + du: display@16460000 { + compatible = "renesas,r9a09g056-du", "renesas,r9a09g057-du"; + reg = <0 0x16460000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + fcpvd: fcp@16470000 { compatible = "renesas,r9a09g056-fcpvd", "renesas,fcpv"; reg = <0 0x16470000 0 0x10000>; From 9a5a73dca92aa120ec1ab8b510eb4dbbd653d4e2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 3 Nov 2025 20:03:49 +0000 Subject: [PATCH 10/41] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable DU and DSI Enable DU, DSI and adv7535 HDMI encoder on RZ/V2N Evaluation Kit. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251103200349.62087-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 066e66b5d51a..4445bebd96c9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -33,6 +33,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -82,12 +93,36 @@ #clock-cells = <0>; clock-frequency = <32768>; }; + + /* 12MHz oscillator for ADV7535 */ + y1: y1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -145,6 +180,40 @@ pinctrl-names = "default"; clock-frequency = <400000>; status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + clocks = <&y1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &i2c6 { From 92279daefc1740961404bca0a7f5149bf6b23dea Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:02 +0000 Subject: [PATCH 11/41] arm64: dts: renesas: r9a09g057: Add USB3 PHY/Host nodes Add USB3 PHY/Host nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index c09578d2c962..a36961804494 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1087,6 +1087,66 @@ status = "disabled"; }; + xhci0: usb@15850000 { + compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + xhci1: usb@15860000 { + compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15860000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xb1>; + power-domains = <&cpg>; + resets = <&cpg 0xab>; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy0: usb-phy@15870000 { + compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G057_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G057_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_phy1: usb-phy@15880000 { + compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15880000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb2>, + <&cpg CPG_CORE R9A09G057_USB3_1_CLKCORE>, + <&cpg CPG_CORE R9A09G057_USB3_1_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xab>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; From 7ef7ba62ec5cd1d32fd282669d0ff947df255408 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:03 +0000 Subject: [PATCH 12/41] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB3.0 PHYs and xHCI controllers Enable the USB3.0 (CH0) and USB3.1 (CH1) host controllers on the RZ/V2H Evaluation Kit. The CN4 stacked connector on the EVK provides access to both channels, with CH0 corresponding to USB3.0 and CH1 to USB3.1. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 90d93116fabd..962a544fc50a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -455,6 +455,16 @@ }; }; + usb30_pins: usb30 { + pinmux = , /* USB30_VBUSEN */ + ; /* USB30_OVRCURN */ + }; + + usb31_pins: usb31 { + pinmux = , /* USB31_VBUSEN */ + ; /* USB31_OVRCURN */ + }; + xspi_pins: xspi0 { ctrl { pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; @@ -521,10 +531,30 @@ status = "okay"; }; +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + &wdt1 { status = "okay"; }; +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xhci1 { + pinctrl-0 = <&usb31_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &xspi { pinctrl-0 = <&xspi_pins>; pinctrl-names = "default"; From 9dd6097c353cf27e1e144d42030867dc8ed4bf56 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:04 +0000 Subject: [PATCH 13/41] arm64: dts: renesas: r9a09g056: Add USB3 PHY/Host nodes Add USB3 PHY/Host nodes to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index c276cdc730bd..ac8b4a4f5fb7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -694,6 +694,36 @@ status = "disabled"; }; + xhci: usb@15850000 { + compatible = "renesas,r9a09g056-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy: usb-phy@15870000 { + compatible = "renesas,r9a09g056-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G056_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G056_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; From f221ce9f7c13ce2c1c9e4fd79743d18fb098f19a Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:05 +0000 Subject: [PATCH 14/41] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB3.0 PHY and xHCI controller Enable the USB3.0 (CH0) host controllers on the RZ/V2N Evaluation Kit. The CN4 connector on the EVK provides access to the USB3.0 channel. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 4445bebd96c9..89154875bb33 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -411,6 +411,11 @@ }; }; + usb3_pins: usb3 { + pinmux = , /* USB30_VBUSEN */ + ; /* USB30_OVRCURN */ + }; + xspi_pins: xspi0 { ctrl { pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; @@ -461,10 +466,20 @@ status = "okay"; }; +&usb3_phy { + status = "okay"; +}; + &wdt1 { status = "okay"; }; +&xhci { + pinctrl-0 = <&usb3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &xspi { pinctrl-0 = <&xspi_pins>; pinctrl-names = "default"; From 40a4c75e7f7170f4dc9f077ae480fe5775a780a1 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 19 Nov 2025 16:35:20 +0200 Subject: [PATCH 15/41] arm64: dts: renesas: r9a08g045: Add PCIe node The RZ/G3S SoC has a variant (R9A08G045S33) which supports PCIe. Add the PCIe node. Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251119143523.977085-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 876de634908e..997e6cf0bb82 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -845,6 +845,71 @@ status = "disabled"; }; + pcie: pcie@11e40000 { + compatible = "renesas,r9a08g045-pcie"; + reg = <0 0x11e40000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names = "aclk", "pm"; + resets = <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + renesas,sysc = <&sysc>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x0033>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 1a66160fb28abcd228f69e00bb183a4749f23805 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 19 Nov 2025 16:35:21 +0200 Subject: [PATCH 16/41] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock Versa3 clock generator available on RZ/G3S SMARC Module provides the reference clock for SoC PCIe interface. Update the device tree to reflect this connection. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251119143523.977085-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 6f25ab617982..982f17aafbc5 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -168,6 +168,11 @@ }; }; +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + #if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 { From 73b73af99a49fd7bf0515741734660973fa2002a Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 19 Nov 2025 16:35:22 +0200 Subject: [PATCH 17/41] arm64: dts: renesas: rzg3s-smarc: Enable PCIe The RZ Smarc Carrier-II board has PCIe headers mounted on it. Enable PCIe support. Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251119143523.977085-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 6b0bb2c441af..70af605168b0 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -155,6 +155,12 @@ status = "okay"; }; +&pcie { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &phyrst { status = "okay"; }; @@ -186,6 +192,11 @@ line-name = "key-3-gpio-irq"; }; + pcie_pins: pcie { + pinmux = , /* PCIE_RST_OUT_B */ + ; /* PCIE_CLKREQ_B */ + }; + scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ From fb8f11c7975ad6096437e6a6757c98c9c9475551 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 19 Nov 2025 18:14:33 +0200 Subject: [PATCH 18/41] arm64: dts: renesas: r9a09g077: Add SPI nodes Add support for the four SPI controllers on the Renesas RZ/T2H Soc. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119161434.595677-13-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index f5fa6ca06409..b0080392f75e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -165,6 +165,78 @@ status = "disabled"; }; + rspi0: spi@80007000 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 104>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@80007400 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 105>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@80007800 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 106>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi3: spi@81007000 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x81007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 602>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, From 3c77f58d108c80c464a0676aeaa3dbf791883f19 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 19 Nov 2025 18:14:34 +0200 Subject: [PATCH 19/41] arm64: dts: renesas: r9a09g087: Add SPI nodes Add support for the four SPI controllers on the Renesas RZ/N2H Soc. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119161434.595677-14-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 361a9235f00d..e273a9aca568 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -165,6 +165,78 @@ status = "disabled"; }; + rspi0: spi@80007000 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 104>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@80007400 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 105>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@80007800 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 106>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi3: spi@81007000 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x81007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 602>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, From 44cfd102ce28e749a07bb0f1668cf932077b1175 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Nov 2025 17:52:06 +0100 Subject: [PATCH 20/41] arm64: dts: renesas: r9a09g047e57-smarc: Remove duplicate SW_LCD_EN SW_LCD_EN is defined twice. Fixes: 9e95446b0cf93a91 ("arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys") Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/1f93558c62f4461f50935644ec831a7d2cb52630.1764089463.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 0fd90d79b020..805c0f67b70d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -8,7 +8,6 @@ /dts-v1/; /* Switch selection settings */ -#define SW_LCD_EN 0 #define SW_GPIO8_CAN0_STB 0 #define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 From b449dbc0bb0301277a6de444901a7122214c090d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:30 +0000 Subject: [PATCH 21/41] arm64: dts: renesas: r9a09g056: Add ICU node Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2N SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index ac8b4a4f5fb7..c72b3b484d05 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -183,12 +183,104 @@ #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g056-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g056-pinctrl"; reg = <0 0x10410000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; gpio-ranges = <&pinctrl 0 0 96>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; From 7d8b4a6672ecaa8540bf4041fea09b5ea6d78070 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:31 +0000 Subject: [PATCH 22/41] arm64: dts: renesas: r9a09g056: Add DMAC nodes Add nodes for the DMAC IPs found on the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 165 +++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index c72b3b484d05..05413551cbb1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -324,6 +324,171 @@ status = "disabled"; }; + dmac0: dma-controller@11400000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x11400000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x0>; + power-domains = <&cpg>; + resets = <&cpg 0x31>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 4>; + }; + + dmac1: dma-controller@14830000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x14830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x1>; + power-domains = <&cpg>; + resets = <&cpg 0x32>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac2: dma-controller@14840000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x14840000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x2>; + power-domains = <&cpg>; + resets = <&cpg 0x33>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac3: dma-controller@12000000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x12000000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x3>; + power-domains = <&cpg>; + resets = <&cpg 0x34>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + + dmac4: dma-controller@12010000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x12010000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x4>; + power-domains = <&cpg>; + resets = <&cpg 0x35>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 3>; + }; + ostm0: timer@11800000 { compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; reg = <0x0 0x11800000 0x0 0x1000>; From 4018dfc222a793f6a4fc5dfb98c883ef3782eb0f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:32 +0000 Subject: [PATCH 23/41] arm64: dts: renesas: r9a09g056: Add RSPI nodes Add nodes for the RSPI IPs found in the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 05413551cbb1..4d37d02138ad 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -664,6 +664,69 @@ status = "disabled"; }; + rspi0: spi@12800000 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x54>, + <&cpg CPG_MOD 0x55>, + <&cpg CPG_MOD 0x56>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7b>, <&cpg 0x7c>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@12800400 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x57>, + <&cpg CPG_MOD 0x58>, + <&cpg CPG_MOD 0x59>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7d>, <&cpg 0x7e>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@12800800 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x5a>, + <&cpg CPG_MOD 0x5b>, + <&cpg CPG_MOD 0x5c>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7f>, <&cpg 0x80>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 41e60d92c88c0085511b38077dad2939bf63ddfc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:33 +0000 Subject: [PATCH 24/41] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support Add support for the NMI connected user pushbutton on the RZ/V2N EVK. The button is wired to the SoC NMI input and can be used to wake the system from low-power states. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 89154875bb33..9af50198d2f1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -8,6 +8,7 @@ /dts-v1/; #include +#include #include "r9a09g056.dtsi" / { @@ -44,6 +45,18 @@ }; }; + keys: keys { + compatible = "gpio-keys"; + + key-wakeup { + interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "NMI_SW"; + debounce-interval = <20>; + wakeup-source; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ From f2d5d0ba4cf7a080a4e42f462cbb1bddceac92c7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 27 Nov 2025 14:13:13 +0100 Subject: [PATCH 25/41] ARM: dts: renesas: r9a06g032: Add Ethernet switch interrupts The Ethernet switch device node still lacks interrupts. Add them. Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Link: https://patch.msgid.link/53d45eed3709cba589a4ef3e9ad198d7e44fd9a5.1764249063.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 8debb77803bb..7c143bd5d7c9 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -453,6 +453,12 @@ <&sysctrl R9A06G032_CLK_SWITCH>; clock-names = "hclk", "clk"; power-domains = <&sysctrl>; + interrupts = , + , + , + , + ; + interrupt-names = "dlr", "switch", "prp", "hub", "ptrn"; status = "disabled"; ethernet-ports { From ef601dbb5b80a0240dc479ca0aa5fbd746f23ca7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 29 Nov 2025 18:51:56 +0000 Subject: [PATCH 26/41] arm64: dts: renesas: r9a09g047: Add RSCI nodes Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251129185203.380002-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 220 +++++++++++++++++++++ 1 file changed, 220 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index d1bf16c6ff6b..cbb48ff5028f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -591,6 +591,226 @@ }; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + wdt1: watchdog@14400000 { compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; From ccf2044987b41dc589de6a86b35d3a4f8ea14762 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 29 Nov 2025 18:51:57 +0000 Subject: [PATCH 27/41] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS SMARC2 board dtsi is common for multiple SoCs. So Move aliases to board DTS as SoC may have different IPs for a given alias. eg: RZ/G3S does not have RSCI interface. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://patch.msgid.link/20251129185203.380002-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 ++++++ arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 805c0f67b70d..50e075745474 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -35,6 +35,12 @@ compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + aliases { + i2c0 = &i2c0; + serial3 = &scif0; + mmc1 = &sdhi1; + }; + vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { compatible = "regulator-gpio"; regulator-name = "SD1_PVDD"; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index 8b3765b8267d..a6e8eb730096 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -37,12 +37,6 @@ stdout-path = "serial3:115200n8"; }; - aliases { - i2c0 = &i2c0; - serial3 = &scif0; - mmc1 = &sdhi1; - }; - can_transceiver0: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; From 835666e7403c3ddc6f3122888d975464f8272efe Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 29 Nov 2025 18:51:58 +0000 Subject: [PATCH 28/41] arm64: dts: renesas: r9a09g047e57-smarc: Enable rsci{2,4,9} nodes Enable device rsci{2,4,9} nodes for the RZ/G3E SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251129185203.380002-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 58 +++++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 7 +++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 4 ++ 3 files changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 50e075745474..696903dc7a63 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -12,6 +12,8 @@ #define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 #define SW_PDM_EN 0 +#define SW_SER0_PMOD 1 +#define SW_SER2_EN 1 #define SW_SD0_DEV_SEL 0 #define SW_SDIO_M2E 0 @@ -37,6 +39,9 @@ aliases { i2c0 = &i2c0; + serial0 = &rsci4; + serial1 = &rsci9; + serial2 = &rsci2; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -140,6 +145,28 @@ input-schmitt-enable; }; + rsci2_pins: rsci2 { + pinmux = , /* RXD2 */ + , /* TXD2 */ + , /* CTS2N */ + ; /* RTS2N */ + bias-pull-up; + }; + + rsci4_pins: rsci4 { + pinmux = , /* RXD4 */ + , /* TXD4 */ + , /* CTS4N */ + ; /* RTS4N */ + bias-pull-up; + }; + + rsci9_pins: rsci9 { + pinmux = , /* RXD9 */ + ; /* TXD9 */ + bias-pull-up; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; @@ -176,6 +203,37 @@ }; }; +#if SW_SER0_PMOD && SW_SER2_EN +&rsci2 { + pinctrl-0 = <&rsci2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) && (SW_SER0_PMOD) +&rsci4 { + pinctrl-0 = <&rsci4_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) +&rsci9 { + pinctrl-0 = <&rsci9_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#endif + &scif0 { pinctrl-0 = <&scif_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index a6e8eb730096..b607b5d6c259 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -13,6 +13,13 @@ * 0 - SMARC SDIO signal is connected to uSD1 * 1 - SMARC SDIO signal is connected to M.2 Key E connector * + * Please set the switch position SW_OPT_MUX.4 on the carrier board and the + * corresponding macro SW_SER0_PMOD on the board DTS: + * + * SW_SER0_PMOD: + * 0 - SER0 signals connect to M.2 Key-E, SER2 signals are unconnected + * 1 - SER0 signals connect to PMOD, SER2 signals connect to M.2 Key-E + * * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the * corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS: * diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 7faa44510d98..eb0de21d6716 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -13,6 +13,10 @@ * 0 - SD0 is connected to eMMC (default) * 1 - SD0 is connected to uSD0 card * + * Switch position SYS.4, Macro SW_SER2_EN: + * 0 - Select Module DSI connector(GPIO) + * 1 - Select SER2 + * * Switch position SYS.5, Macro SW_LCD_EN: * 0 - Select Misc. Signals routing * 1 - Select LCD From f060bbe2c32941acc4738cc27039246593f49a33 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 1 Dec 2025 13:29:32 +0200 Subject: [PATCH 29/41] arm64: dts: renesas: r9a09g077: Add ICU support The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251201112933.488801-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index b0080392f75e..63de8271f47c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -828,6 +828,79 @@ #power-domain-cells = <0>; }; + icu: interrupt-controller@802a0000 { + compatible = "renesas,r9a09g077-icu"; + reg = <0 0x802a0000 0 0x10000>, + <0 0x812a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "intcpu0", "intcpu1", "intcpu2", + "intcpu3", "intcpu4", "intcpu5", + "intcpu6", "intcpu7", "intcpu8", + "intcpu9", "intcpu10", "intcpu11", + "intcpu12", "intcpu13", "intcpu14", + "intcpu15", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "sei", + "ca55-err0", "ca55-err1", + "cr520-err0", "cr520-err1", + "cr521-err0", "cr521-err1", + "peri-err0", "peri-err1", + "dsmif-err0", "dsmif-err1", + "encif-err0", "encif-err1"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + power-domains = <&cpg>; + }; + pinctrl: pinctrl@802c0000 { compatible = "renesas,r9a09g077-pinctrl"; reg = <0 0x802c0000 0 0x10000>, From d42c64cf161644929de081e541afbab33acb231a Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 1 Dec 2025 13:29:33 +0200 Subject: [PATCH 30/41] arm64: dts: renesas: r9a09g087: Add ICU support The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251201112933.488801-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index e273a9aca568..9809a6a9c1c0 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -831,6 +831,79 @@ #power-domain-cells = <0>; }; + icu: interrupt-controller@802a0000 { + compatible = "renesas,r9a09g087-icu", "renesas,r9a09g077-icu"; + reg = <0 0x802a0000 0 0x10000>, + <0 0x812a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "intcpu0", "intcpu1", "intcpu2", + "intcpu3", "intcpu4", "intcpu5", + "intcpu6", "intcpu7", "intcpu8", + "intcpu9", "intcpu10", "intcpu11", + "intcpu12", "intcpu13", "intcpu14", + "intcpu15", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "sei", + "ca55-err0", "ca55-err1", + "cr520-err0", "cr520-err1", + "cr521-err0", "cr521-err1", + "peri-err0", "peri-err1", + "dsmif-err0", "dsmif-err1", + "encif-err0", "encif-err1"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + power-domains = <&cpg>; + }; + pinctrl: pinctrl@802c0000 { compatible = "renesas,r9a09g087-pinctrl"; reg = <0 0x802c0000 0 0x10000>, From 50f51092bff57a143906a428056ff103fa75ef21 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:12:53 +0200 Subject: [PATCH 31/41] arm64: dts: renesas: r9a09g077: Add DMAC support The Renesas RZ/T2H (R9A09G077) SoC has three instances of the DMAC IP. Add support for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205151254.2970669-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 63de8271f47c..2db5f5e94f7c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -342,6 +342,96 @@ status = "disabled"; }; + dmac0: dma-controller@800c0000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c0000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac1: dma-controller@800c1000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c1000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac2: dma-controller@800c2000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c2000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + gmac0: ethernet@80100000 { compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; reg = <0 0x80100000 0 0x10000>; From 57a0c2d36c646a64c117de534b787abe0a0b8bcf Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:12:54 +0200 Subject: [PATCH 32/41] arm64: dts: renesas: r9a09g087: Add DMAC support The Renesas RZ/N2H (R9A09G087) SoC has three instances of the DMAC IP. Add support for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205151254.2970669-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 9809a6a9c1c0..f3225694b4cb 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -342,6 +342,96 @@ status = "disabled"; }; + dmac0: dma-controller@800c0000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c0000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac1: dma-controller@800c1000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c1000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac2: dma-controller@800c2000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c2000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + gmac0: ethernet@80100000 { compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; From f3d22e5f6392d05d61438455bce40bfb766bf2b4 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 9 Dec 2025 09:11:15 +0000 Subject: [PATCH 33/41] arm64: dts: renesas: r9a09g056: Add TSU nodes The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251209091115.8541-4-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 4d37d02138ad..d942ac1f7865 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -83,6 +83,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -93,6 +94,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -103,6 +105,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -113,6 +116,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -303,6 +307,32 @@ resets = <&cpg 0x30>; }; + tsu0: thermal@11000000 { + compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x11000000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x109>; + resets = <&cpg 0xf7>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x320>; + }; + + tsu1: thermal@14002000 { + compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x14002000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; + xspi: spi@11030000 { compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi"; reg = <0 0x11030000 0 0x10000>, @@ -1403,6 +1433,51 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + sensor1_thermal: sensor1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor2_thermal: sensor2-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu1>; + + cooling-maps { + map0 { + trip = <&sensor2_target>; + cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution = <1024>; + }; + }; + + trips { + sensor2_target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From 556a9d46fd8a5e4455b594570ad01152cb0381be Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:13:18 +0900 Subject: [PATCH 34/41] arm64: dts: renesas: r8a77980: Add SWDT node Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215031318.2219-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 8cd7f68d026b..0e81bef180a0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -139,6 +139,15 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77980_CLK_OSC>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77980", "renesas,rcar-gen3-gpio"; From cb12cfa7f650cfa315994a43ce7f795f62d19e15 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:13:19 +0900 Subject: [PATCH 35/41] arm64: dts: renesas: condor/v3hsk: Mark SWDT as reserved This watchdog can't be used with Linux because the firmware needs it on R-Car V3H boards. Sadly, it doesn't mark the node as reserved, so this is added manually here. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215031318.2219-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/condor-common.dtsi | 5 +++++ arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 9fe9c722187d..38d486e7b8c3 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -554,3 +554,8 @@ &scif_clk { clock-frequency = <14745600>; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index 2da63b4daa0a..87a9bb44cad6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -289,3 +289,8 @@ &scif_clk { clock-frequency = <14745600>; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; From 860d9b042c5d99dacb76f29ea79b74e9a0a1ea84 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:15 +0900 Subject: [PATCH 36/41] arm64: dts: renesas: r8a77970: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1007ee48adc3..1f6676e2795a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1209,6 +1209,38 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a77970-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77970_CLK_R>, + <&cpg CPG_CORE R8A77970_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 325>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a77970-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77970_CLK_R>, + <&cpg CPG_CORE R8A77970_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 324>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 84e41ebccda4577ac9b41040b265e27c8905215d Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:16 +0900 Subject: [PATCH 37/41] arm64: dts: renesas: r8a77980: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-10-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 0e81bef180a0..86b7792d68fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1591,6 +1591,86 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 325>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 324>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 321>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 309>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 403>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 65be6f4a468c9005b6b28d9fcae21f12a97b9086 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:17 +0900 Subject: [PATCH 38/41] arm64: dts: renesas: r8a779a0: Add WWDT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested-by: Niklas Söderlund Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-11-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 160 ++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 4b101a6dc49d..0483a5d0714a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -3032,6 +3032,166 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1200>, <&cpg 1318>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1201>, <&cpg 1319>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1202>, <&cpg 1320>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1203>, <&cpg 1321>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1204>, <&cpg 1322>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1205>, <&cpg 1323>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1206>, <&cpg 1324>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt7: watchdog@fff20000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff20000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1207>, <&cpg 1325>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt8: watchdog@fff30000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff30000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1208>, <&cpg 1326>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt9: watchdog@fff40000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff40000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1209>, <&cpg 1327>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From b7c182ff3218ca31f97d102e6c958d184159eb1e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:18 +0900 Subject: [PATCH 39/41] arm64: dts: renesas: r8a779f0: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-12-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 160 ++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 0ebf8e5dd2f9..cbb161c863ac 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1297,6 +1297,166 @@ interrupts = ; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1200>, <&cpg 1318>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1201>, <&cpg 1319>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1202>, <&cpg 1320>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1203>, <&cpg 1321>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1204>, <&cpg 1322>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1205>, <&cpg 1323>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1206>, <&cpg 1324>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt7: watchdog@fff20000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff20000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1207>, <&cpg 1325>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt8: watchdog@fff30000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff30000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1208>, <&cpg 1326>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt9: watchdog@fff40000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff40000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1209>, <&cpg 1327>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 2dc4f97074c867e823f3f8b08f04e7d031a8acad Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:19 +0900 Subject: [PATCH 40/41] arm64: dts: renesas: r8a779g0: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-13-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 112 ++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index ff2bd1908a45..82a7278836e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2544,6 +2544,118 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1200>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1201>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1202>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1203>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1204>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1205>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1206>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From aca3bbde0fdb263081b5ff1e60f066704dd1a19e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:20 +0900 Subject: [PATCH 41/41] arm64: dts: renesas: r8a779h0: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-14-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 112 ++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 4dc0e5304f72..74bc4c4854ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -2183,6 +2183,118 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1200>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1201>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1202>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1203>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1204>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1205>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1206>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>;