From aa8faabadc59005c4c087f6e3642b5c6a05c2c96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 12 Jun 2026 20:36:50 +0300 Subject: [PATCH] drm/i915/cdclk: Clean up CDCLK_CTL defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the modern REG_BIT/REG_GENMASK stuff to define the CDCLK_CTL bits. Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260612173653.7830-4-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak --- .../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index bb7329c8964c..7088ab7ea030 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -2771,7 +2771,7 @@ enum skl_power_gate { #define CDCLK_CTL _MMIO(0x46000) #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) -#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) +#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) #define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25) @@ -2782,15 +2782,18 @@ enum skl_power_gate { #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) -#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) -#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) -#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) -#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) -#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) -#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) -#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE -#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) -#define CDCLK_FREQ_DECIMAL_MASK (0x7ff) +#define BXT_CDCLK_CD2X_PIPE_MASK REG_GENMASK(21, 20) +#define BXT_CDCLK_CD2X_PIPE(pipe) REG_FIELD_PREP(BXT_CDCLK_CD2X_PIPE_MASK, (pipe)) +#define BXT_CDCLK_CD2X_PIPE_NONE REG_FIELD_PREP(BXT_CDCLK_CD2X_PIPE_MASK, 3) +#define ICL_CDCLK_CD2X_PIPE_MASK REG_GENMASK(21, 19) +#define ICL_CDCLK_CD2X_PIPE(pipe) REG_FIELD_PREP(ICL_CDCLK_CD2X_PIPE_MASK, _PICK((pipe), 0, 1, 3) << 1) +#define ICL_CDCLK_CD2X_PIPE_NONE REG_FIELD_PREP(ICL_CDCLK_CD2X_PIPE_MASK, 7) +#define TGL_CDCLK_CD2X_PIPE_MASK REG_GENMASK(21, 19) +#define TGL_CDCLK_CD2X_PIPE(pipe) REG_FIELD_PREP(TGL_CDCLK_CD2X_PIPE_MASK, (pipe) << 1) +#define TGL_CDCLK_CD2X_PIPE_NONE REG_FIELD_PREP(TGL_CDCLK_CD2X_PIPE_MASK, 7) +#define CDCLK_DIVMUX_CD_OVERRIDE REG_BIT(19) +#define BXT_CDCLK_SSA_PRECHARGE_ENABLE REG_BIT(16) +#define CDCLK_FREQ_DECIMAL_MASK REG_GENMASK(10, 0) /* CDCLK_SQUASH_CTL */ #define CDCLK_SQUASH_CTL _MMIO(0x46008)