ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi

No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Lucas Stach 2013-01-22 22:46:07 +01:00 • committed by Stephen Warren
commit ab343e91aa
8 changed files with 5 additions and 8 deletions