PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller

Browse source

Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP.

[bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap
error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix]
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>

...

This commit is contained in:

Bharat Kumar Gogada 2016-03-06 22:02:14 +05:30 • committed by Bjorn Helgaas

parent 92e963f50f

commit ab597d35ef

4 changed files with 960 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

68

Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt

View file

10

drivers/pci/host/Kconfig

View file

1

drivers/pci/host/Makefile

View file

881

drivers/pci/host/pcie-xilinx-nwl.c

View file