clk: sunxi: Add H3 clocks support

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The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Jens Kuske 2015-12-04 22:24:40 +01:00 • committed by Maxime Ripard

parent 6d3a47c291

commit ab6e23a4e3

4 changed files with 121 additions and 0 deletions

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2

Documentation/devicetree/bindings/clock/sunxi.txt

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1

drivers/clk/sunxi/Makefile

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112

drivers/clk/sunxi/clk-sun8i-bus-gates.c

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6

drivers/clk/sunxi/clk-sunxi.c

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