drm/amd/display: refactor clk_resync to avoid assertion

Browse source

- not all DCE has PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE bit defined.

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Tony Cheng 2017-01-16 20:37:08 -05:00 • committed by Alex Deucher

parent 534db19886

commit ab7044d0d1

1 changed files with 30 additions and 27 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

57

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

View file