powerpc/e500mc: flush L2 on NAP for e500mc

Browse source

If we have an L2CSR register (e500mc) we need to flush the L2 before going
to nap.  We use the HW flush mechanism provided in that register.

The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
any code in the kernel.  Additionally we didn't reuse the exist L2CR
feature bit as this is intended for the 7xxx L2CR register and L2CSR
is part of the new Freescale "Book-E" registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

...

This commit is contained in:

Kumar Gala 2008-06-19 09:40:31 -05:00

parent fc4033b2f8

commit aba11fc50c

3 changed files with 30 additions and 4 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

8

include/asm-powerpc/cputable.h

View file

17

include/asm-powerpc/reg_booke.h

View file