RISC-V: fix vector insn load/store width mask

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[ Upstream commit 04a2aef59c ]

RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
Replace GENMASK(3, 0) with GENMASK(2, 0).

Fixes: cd05483724 ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240606182800.415831-1-jesse@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Jesse Taube 2024-06-06 14:28:00 -04:00 • committed by Greg Kroah-Hartman

parent 2d83492259

commit abb84c4620

1 changed files with 1 additions and 1 deletions

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arch/riscv/include/asm/insn.h

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