ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi

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No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

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This commit is contained in:

Stephen Warren 2013-01-23 09:43:49 -07:00

parent bf5fcc76d3

commit abf80c276d

3 changed files with 5 additions and 3 deletions

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1

arch/arm/boot/dts/tegra30-beaver.dts

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2

arch/arm/boot/dts/tegra30-cardhu.dtsi

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5

arch/arm/boot/dts/tegra30.dtsi

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