clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

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Up until the these limits were global/hard-coded, since they are typically
limits of the fabric.

However, since this is an FPGA generated clock, this may run on setups
where one clock is on a fabric, and another one synthesized on another
fabric connected via PCIe (or some other inter-connect, and then these
limits need to be adjusted for each instance of the AXI CLKGEN.

This change wraps the current constants in 'axi_clkgen_limits' struct and
the 'axi_clkgen' instance keeps a copy of these limits, which is
initialized at probe from the default limits.

The limits are stored on the device-tree OF table, so that we can adjust
them via the compatible string.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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This commit is contained in:

Alexandru Ardelean 2020-12-03 09:40:36 +02:00 • committed by Stephen Boyd

parent bd91abb218

commit ac1ee86a9c

1 changed files with 31 additions and 17 deletions

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drivers/clk/clk-axi-clkgen.c

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