drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a

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A side-effect of commit 7d54a90428
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Aug 10 10:18:10 2012 +0100

    drm/i915: Apply post-sync write for pipe control invalidates

was that only a request to emit invalidate flush would result in the
TLB being invalidated (since it requires synchronisation and so incurs a
performance penalty). However, the stated w/a for hardware contexts is
that the TLBs must be invalidated prior to a MI_SET_CONTEXT, yet the w/a
itself did not request the TLBs to be invalidated...

Note this w/a does not prevent the hard system hang I experience when
using hw contexts (with rc6 enabled) on SNB GT1.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Chris Wilson 2012-10-01 14:27:04 +01:00 • committed by Daniel Vetter

parent 3bc2913e2c

commit ac82ea2e97

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/i915_gem_context.c

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