riscv,entry: fix misaligned base for excp_vect_table

Browse source

In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

...

This commit is contained in:

Zihao Yu 2021-03-17 16:17:25 +08:00 • committed by Palmer Dabbelt

parent 285a76bb2c

commit ac8d0b901f

No known key found for this signature in database

GPG key ID: 2E1319F35FBB1889

1 changed files with 1 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

1

arch/riscv/kernel/entry.S

View file