perf vendor events riscv: Add SiFive Bullet version 0x07 events

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SiFive Bullet microarchitecture cores with mimpid values starting with
0x07 or greater add new PMU events to support debug, trace, and counter
sampling and filtering (Sscofpmf).

All other PMU events are unchanged from earlier Bullet cores.

Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Tested-by: Ian Rogers <irogers@google.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250213220341.3215660-5-samuel.holland@sifive.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

...

This commit is contained in:

Eric Lin 2025-02-12 17:21:37 -08:00 • committed by Namhyung Kim

parent 4f762cb409

commit acaefd6049

7 changed files with 120 additions and 0 deletions

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tools/perf/pmu-events/arch/riscv/mapfile.csv

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1 # Format: 15 # 16 #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType 17 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core 18 0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core 19 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 20 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 21 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core

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tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json

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tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json Symbolic link

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tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json Symbolic link

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tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json Symbolic link

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tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json

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tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json

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