From acef787228d7e8fd57cb6a2e8681e5be97b033b9 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Mon, 14 Sep 2026 13:51:32 -0500 Subject: [PATCH] drm/amdgpu: disable XNACK replay for all VMIDs on GC 12.1.0 A0 XNACK is not supported on A0. Updating RETRY_DISABLE only for the VMID in use gives unreliable control, so all VMIDs must be programmed identically. Set SH_MEM_CONFIG.RETRY_DISABLE = 1 on rev_id 0 for every VMID in both constants init and compute VMID init, so XNACK replay is off from device boot up. Signed-off-by: Alex Sierra Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 20 ++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 17 ----------------- drivers/gpu/drm/amd/amdgpu/soc_v1_0.h | 22 ++++++++++++++++++++++ 3 files changed, 40 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index db541939555b..f5b6d6989289 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -1496,11 +1496,23 @@ static u32 gfx_v12_1_get_sa_active_bitmap(struct amdgpu_device *adev, return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); } +static u32 gfx_v12_1_get_sh_mem_config(struct amdgpu_device *adev) +{ + u32 sh_mem_config = DEFAULT_SH_MEM_CONFIG; + + /* GC 12.1.0 A0 requires RETRY_DISABLE in SH_MEM_CONFIG. */ + if (SOC_V1_0_DIE_REV_XCD(adev->rev_id) == 0) + sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; + + return sh_mem_config; +} + static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, int xcc_id) { int i; uint32_t sh_mem_bases; + uint32_t sh_mem_config; uint32_t data; /* @@ -1512,12 +1524,13 @@ static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, (adev->gmc.private_aperture_start >> 58)); sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE, (adev->gmc.shared_aperture_start >> 48)); + sh_mem_config = gfx_v12_1_get_sh_mem_config(adev); mutex_lock(&adev->srbm_mutex); for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); /* CP and shaders */ - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); /* Enable trap for each kfd vmid. */ @@ -1551,8 +1564,11 @@ static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, int xcc_id) { u32 tmp; + u32 sh_mem_config; int i; + sh_mem_config = gfx_v12_1_get_sh_mem_config(adev); + /* XXX SH_MEM regs */ /* where to put LDS, scratch, GPUVM in FSA64 space */ mutex_lock(&adev->srbm_mutex); @@ -1560,7 +1576,7 @@ static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); /* CP and shaders */ WREG32_SOC15(GC, GET_INST(GC, xcc_id), - regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); + regSH_MEM_CONFIG, sh_mem_config); if (i != 0) { tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, (adev->gmc.private_aperture_start >> 58)); diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index 28eca48c6596..506060fc5368 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -49,23 +49,6 @@ #define NORMALIZE_MID_REG_OFFSET(offset) \ (offset & 0x3FFFF) -/* - * die_info[0].die_id from IP discovery encodes the silicon revision: - * bit[15:12] Reserved - * bit[11:8] MID revision - * bit[7:4] AID revision - * bit[3:0] XCD revision - * The value is copied into adev->rev_id[15:0] (rev_id[31:16] are 0) and mapped - * to adev->external_rev_id below. - */ -#define SOC_V1_0_DIE_REV_XCD__SHIFT 0 -#define SOC_V1_0_DIE_REV_AID__SHIFT 4 -#define SOC_V1_0_DIE_REV_MID__SHIFT 8 -#define SOC_V1_0_DIE_REV(mid, aid, xcd) \ - (((mid) << SOC_V1_0_DIE_REV_MID__SHIFT) | \ - ((aid) << SOC_V1_0_DIE_REV_AID__SHIFT) | \ - ((xcd) << SOC_V1_0_DIE_REV_XCD__SHIFT)) - static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = { .codec_count = 0, .codec_array = NULL, diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h index 82752964d2c1..9bff7cc60121 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h @@ -25,6 +25,28 @@ extern const struct amdgpu_ip_block_version soc_v1_0_common_ip_block; +/* + * die_info[0].die_id from IP discovery encodes the silicon revision: + * bit[15:12] Reserved + * bit[11:8] MID revision + * bit[7:4] AID revision + * bit[3:0] XCD revision + * The value is copied into adev->rev_id[15:0] (rev_id[31:16] are 0) and mapped + * to adev->external_rev_id in soc_v1_0_set_rev_id(). + */ +#define SOC_V1_0_DIE_REV_XCD__SHIFT 0 +#define SOC_V1_0_DIE_REV_XCD__MASK 0x00f +#define SOC_V1_0_DIE_REV_AID__SHIFT 4 +#define SOC_V1_0_DIE_REV_AID__MASK 0x0f0 +#define SOC_V1_0_DIE_REV_MID__SHIFT 8 +#define SOC_V1_0_DIE_REV_MID__MASK 0xf00 +#define SOC_V1_0_DIE_REV(mid, aid, xcd) \ + (((mid) << SOC_V1_0_DIE_REV_MID__SHIFT) | \ + ((aid) << SOC_V1_0_DIE_REV_AID__SHIFT) | \ + ((xcd) << SOC_V1_0_DIE_REV_XCD__SHIFT)) +#define SOC_V1_0_DIE_REV_XCD(rev_id) \ + (((rev_id) & SOC_V1_0_DIE_REV_XCD__MASK) >> SOC_V1_0_DIE_REV_XCD__SHIFT) + void soc_v1_0_grbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid,