irqchip/qcom-pdc: Configure PDC to pass through mode

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All PDC hardware versions support pass-through mode in which both Direct
SPIs and GPIO interrupts (as SPIs) are sent to the GIC without latching at
the PDC level.

Newer PDCs (v3.0 onwards) also support an additional secondary controller
mode where PDC latches the GPIO interrupts and sends them to the GIC as
level type interrupts. Direct SPIs works the same as pass-through mode
without latching at PDC even in secondary controller mode.

All the SoCs use pass-through mode with the exception of x1e. The x1e PDC
may be set to secondary controller mode for builds on CRD boards whereas it
may be set to pass through mode for IoT-EVK boards. The mode configuration
is done in firmware and initially shipped windows firmware did not have a
SCM interface to read or modify the PDC mode. Only later write access was
opened up for the non-secure world. The availability of write access can be
probed.

Therefore try to modify the to modify the PDC mode to pass-through mode via
SCM write. When the write fails on older firmware assume it to work in
secondary mode.

In secondary mode set the separate irqchip for the GPIOs to perform
additional operations only for the GPIO interrupts.

[ tglx: Massage change log ]

Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-4-dfd1f4a3ae89@oss.qualcomm.com

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This commit is contained in:

Maulik Shah 2026-07-07 14:51:36 +05:30 • committed by Thomas Gleixner

parent 45af2d61ed

commit ad01c2b2f2

1 changed files with 227 additions and 13 deletions

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drivers/irqchip/qcom-pdc.c

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