drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI

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The PCH transcoder registers are only 12 bits wide for the hdisplay
and hblank_start values. On HSW/BDW the CPU side registers are 13
bits wide. intel_mode_valid() only checks against the higher limit
(since we don't know where the mode is to be used), so an extra
check is required against the FDI limits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-3-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

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Ville Syrjälä 2018-06-15 20:44:06 +03:00

parent ad77c537ea

commit ad193bc620

1 changed files with 9 additions and 0 deletions

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drivers/gpu/drm/i915/intel_crt.c

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