ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP

SmartReflex AVS Errorgen module supplies signals to Voltage
Processor. It is suggested that by disabling Errorgen module
before we disable VP, we might be able to ensure lesser
chances of race condition to occur in the system.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
This commit is contained in:
Nishanth Menon 2012-02-29 23:33:39 +01:00 • committed by Kevin Hilman
commit ad54c3ddb4
3 changed files with 46 additions and 0 deletions