sfc_ef100: read Design Parameters at probe time

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Several parts of the EF100 architecture are parameterised (to allow
 varying capabilities on FPGAs according to resource constraints), and
 these parameters are exposed to the driver through a TLV-encoded
 region of the BAR.
For the most part we either don't care about these values at all or
 just need to sanity-check them against the driver's assumptions, but
 there are a number of TSO limits which we record so that we will be
 able to check against them in the TX path when handling GSO skbs.

Signed-off-by: Edward Cree <ecree@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Edward Cree 2020-08-03 21:33:20 +01:00 • committed by David S. Miller

parent 4496363bec

commit adcfc3482f

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216

drivers/net/ethernet/sfc/ef100_nic.c

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4

drivers/net/ethernet/sfc/ef100_nic.h

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