ASoC: da7218: Update PLL ranges and dividers to improve locking

The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Adam Thomson 2016-04-22 14:16:26 +01:00 • committed by Mark Brown
commit ae48a35c40
2 changed files with 28 additions and 25 deletions