spi: cadence-qspi: Add a flag for controllers without indirect access support

Browse source

Renesas RZ/N1 QSPI controllers embed the Cadence IP with some
limitations/simplifications. One of the is that only direct access is
supported, none of the registers related to indirect writes are
populated, so create a flag to avoid these accesses and make sure only
direct accessors are called.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Tested-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://patch.msgid.link/20260122-schneider-6-19-rc1-qspi-v4-11-f9c21419a3e6@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

...

This commit is contained in:

Miquel Raynal (Schneider Electric) 2026-01-22 16:13:36 +01:00 • committed by Mark Brown

parent 612227b392

commit ae62e7cf6a

No known key found for this signature in database

GPG key ID: 24D68B725D5487D0

1 changed files with 16 additions and 13 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

29

drivers/spi/spi-cadence-quadspi.c

View file