drm/i915: Fix CHV DSI PLL refclk during state readout

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Use the proper refclock frequency (100MHz) when reading out the
current DSI clock on CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-13-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

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Ville Syrjälä 2016-03-15 16:40:05 +02:00

parent f00b56896e

commit ae9ec62bda

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/intel_dsi_pll.c

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