ASoC: Intel: bytcr_rt5651: Configure PLL1 before using it

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When platform_clock_control() first selects PLL1 as sysclk the PLL_CTRL
registers have not been setup yet and we effectively have an invalid clock
configuration until byt_rt5651_aif1_hw_params() gets called.

Add a new byt_rt5651_prepare_and_enable_pll1() helper and use that from
both platform_clock_control() and byt_rt5651_aif1_hw_params() to fix this.

Tested-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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Hans de Goede 2018-03-04 15:36:03 +01:00 • committed by Mark Brown

parent 8ffaa6a136

commit aeec6cc082

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sound/soc/intel/boards/bytcr_rt5651.c

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