riscv: Do not fail to build on byte/halfword operations with Zawrs

Browse source

riscv does not have lr instructions on byte and halfword but the
qspinlock implementation actually uses such atomics provided by the
Zabha extension, so those sizes are legitimate.

Then instead of failing to build, just fallback to the !Zawrs path.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

...

This commit is contained in:

Alexandre Ghiti 2024-11-03 15:51:42 +01:00 • committed by Palmer Dabbelt

parent 010e12aa49

commit af042c457d

No known key found for this signature in database

GPG key ID: 2E1319F35FBB1889

1 changed files with 5 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

5

arch/riscv/include/asm/cmpxchg.h

View file