i.MX clocks changes for 6.11

Browse source

- Add reset controller support to audiomix block control
 - Add CLK_SET_RATE_PARENT flag to all audiomix clocks and to
   i.MX7D lcdif_pixel_src clock
 - Fix parent clocks for earc_phy and audpll on i.MX8MP
 - Fix default parents for enet[12]_ref_sel on i.MX6UL
 - Add ops in composite 8M and 93 that allow no-op on disable
 - Add check for PCC present bit on composite 7ULP register
 - Fix fractional part for fracn-gppll on prepare
 - Fix clock tree update for TF-A managed clocks on i.MX8M
 - Drop CLK_SET_PARENT_GATE for DRAM mux on i.MX7D
 - Add the SAI7 IPG clock for i.MX8MN
 - Mark the 'nand_usdhc_bus' clock as non-critical on i.MX8MM
 - Add LVDS bypass clocks on i.MX8QXP
 - Add muxes for MIPI and PHY ref clocks
 - Reorder dc0_bypass0_clk, lcd_pxl and dc1_disp clocks on i.MX8QXP
 - Add 1039.5MHz and 800MHz rates to fracn-gppll table
 - Add CLK_SET_RATE_PARENT for media_disp pixel clocks on i.MX8QXP
 - Add some module descriptions to the i.MX generic and the
   i.MXRT1050 driver.
 - Fix return value for bypass for composite 7ULP
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEETvPuEU56jyrKp9G4G19EyQCVFVYFAmaC8eAACgkQG19EyQCV
 FVYiIBAAw620DeNjzNhKtQzlESdfk5lEW2FkRbJptJk0iFvWUtdNZPIkYb9Q4LEi
 bXLdZ8jardRdDbaf7yNjMuiQnQZv5faJfRMoyp5dHuVl/wRVWA/5rEQHKrj4v9i9
 CrpBsxXk4DAItYJtrty0C8x3rZn1K4Fn50Y2OL9w9cDYFhSJaLaYRV0lt0TRO5O/
 EO8690FJd5GvSUgiWDgtPpkiQgWTN1A1stEqYazc5DjeOFt3ipmFtyrVF42E9bZK
 8W5aNqkt/ukRFKyFUeLIPUck6GVp9ZXgRcnAQKS8NKGlLdnnHCd3/61jr5LMLdGt
 rpWRkq9iQCYOzpGMV+TFt/I6G4u5xEMzo9dkb+iuEEzw9Fh2TXdGUkVS+32hhXDc
 STjQwjsaLv0gu1d4XHi/5G5+M70bNk10aTFKBIYuH0/BFPQ0yu2C3LgJVqC57pGX
 3oR9uNTY9vJoT+OecGW4kLNOHhnGO2InY/SRHwyTR3zVqCsWoBpyxRGNqpH+0Ktr
 ZOIFqfAg0d8Veeiswk67R+2XljC2plVh9rfWFg5BG5zWf+BuqyoGffdD8W6bL5aT
 LhYa9oTBgxehhAk5o75uC3j+PaV+aNfNolzioxSNaJExaxf2O5BLkM3VpcBVVAFB
 +9a4EP4At9nmyAzhQRMbq5cUS2SxuP2GP50d9KwVxxOwswy6aw8=
 =lDKa
 -----END PGP SIGNATURE-----

Merge tag 'clk-imx-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Add reset controller support to audiomix block control
 - Add CLK_SET_RATE_PARENT flag to all audiomix clocks and to
   i.MX7D lcdif_pixel_src clock
 - Fix parent clocks for earc_phy and audpll on i.MX8MP
 - Fix default parents for enet[12]_ref_sel on i.MX6UL
 - Add ops in composite 8M and 93 that allow no-op on disable
 - Add check for PCC present bit on composite 7ULP register
 - Fix fractional part for fracn-gppll on prepare
 - Fix clock tree update for TF-A managed clocks on i.MX8M
 - Drop CLK_SET_PARENT_GATE for DRAM mux on i.MX7D
 - Add the SAI7 IPG clock for i.MX8MN
 - Mark the 'nand_usdhc_bus' clock as non-critical on i.MX8MM
 - Add LVDS bypass clocks on i.MX8QXP
 - Add muxes for MIPI and PHY ref clocks
 - Reorder dc0_bypass0_clk, lcd_pxl and dc1_disp clocks on i.MX8QXP
 - Add 1039.5MHz and 800MHz rates to fracn-gppll table
 - Add CLK_SET_RATE_PARENT for media_disp pixel clocks on i.MX8QXP
 - Add some module descriptions to the i.MX generic and the
   i.MXRT1050 driver.
 - Fix return value for bypass for composite 7ULP

* tag 'clk-imx-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (22 commits)
  clk: imx: composite-7ulp: Use NULL instead of 0
  clk: imx: add missing MODULE_DESCRIPTION() macros
  clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
  clk: imx: fracn-gppll: update rate table
  clk: imx: imx8qxp: Parent should be initialized earlier than the clock
  clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
  clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
  clk: imx: imx8qxp: Add LVDS bypass clocks
  clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
  clk: imx: imx8mn: add sai7_ipg_clk clock settings
  clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
  clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
  clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
  clk: imx: fracn-gppll: fix fractional part of PLL getting lost
  clk: imx: composite-7ulp: Check the PCC present bit
  clk: imx: composite-93: keep root clock on when mcore enabled
  clk: imx: composite-8m: Enable gate clk with mcore_booted
  clk: imx: imx6ul: fix default parent for enet*_ref_sel
  clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll
  clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks
  ...

...

This commit is contained in:

Stephen Boyd 2024-07-01 13:25:33 -07:00

parent 1613e604df 466da3d2d9

commit af05917c22

16 changed files with 197 additions and 52 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

3

Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml

View file

1

drivers/clk/imx/Kconfig

View file

7

drivers/clk/imx/clk-composite-7ulp.c

View file

51

drivers/clk/imx/clk-composite-8m.c

View file

15

drivers/clk/imx/clk-composite-93.c

View file

6

drivers/clk/imx/clk-fracn-gppll.c

View file

4

drivers/clk/imx/clk-imx6ul.c

View file

6

drivers/clk/imx/clk-imx7d.c

View file

2

drivers/clk/imx/clk-imx8mm.c

View file

1

drivers/clk/imx/clk-imx8mn.c

View file

86

drivers/clk/imx/clk-imx8mp-audiomix.c

View file

8

drivers/clk/imx/clk-imx8mp.c

View file

51

drivers/clk/imx/clk-imx8qxp.c

View file

1

drivers/clk/imx/clk-imxrt1050.c

View file

1

drivers/clk/imx/clk.c

View file

4

drivers/clk/imx/clk.h

View file