spi-cadence: support transmission with

Merge series from Jun Guo <jun.guo@cixtech.com>:

The Cadence SPI IP supports configurable FIFO data widths during
integration. On some SoCs, the FIFO data width is designed to be 16 or
32 bits at the chip design stage. However, the current driver only
supports communication with an 8-bit FIFO data width. Therefore, these
patches are added to enable the driver to support communication with
16-bit and 32-bit FIFO data widths.
This commit is contained in:
Mark Brown 2025-11-14 14:47:49 +00:00
commit af330925a1
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245 changed files with 2139 additions and 937 deletions

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