drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts

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Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.

How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW.

Signed-off-by: Danijel Slivka <danijel.slivka@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Danijel Slivka 2024-06-24 07:58:24 +02:00 • committed by Alex Deucher

parent bf826ba9b4

commit afbf7955ff

1 changed files with 28 additions and 0 deletions

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drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

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