clk: tegra: pll: Fix issues with rates for VCO PLLs

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Without this change clk_get_rate would return the final output
rather than the VCO output as it would factor in the pdiv when
it shouldn't. This will cause problems for all dividers in the
subtree of the VCO PLL.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Andrew Bresticker 2015-06-18 17:28:37 -04:00 • committed by Thierry Reding

parent 6b301a059e

commit afff455cf4

1 changed files with 12 additions and 4 deletions

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drivers/clk/tegra/clk-pll.c

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