drm/amd/display: Workaround required for link training reliability

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[Why]
A software workaround is required for all vendor-built cards on platform.

[How]
When performing DP link training, we must send TPS1 before DPCD:100h is
written with the proper bit rate value. This change must be applies in
ALL cases when LT happens.

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

David Galiffi 2020-01-29 17:02:32 -05:00 • committed by Alex Deucher

parent 31cf6f3593

commit b01f22ec88

2 changed files with 19 additions and 1 deletions

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19

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

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1

drivers/gpu/drm/amd/display/dc/dc_link.h

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