arm64: dts: ti: Add USB Type C swap defines for J721S2 SoC

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Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C
lane swap. Update the macro definition for it.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230921100039.19897-2-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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Sinthu Raja 2023-09-21 15:30:37 +05:30 • committed by Vignesh Raghavendra

parent c2e7258dbd

commit b024d1a853

1 changed files with 1 additions and 1 deletions

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arch/arm64/boot/dts/ti/k3-serdes.h

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