drm/i915/dp: Enable SST fallback between UHBR and non-UHBR rates

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Enable link training fallback between UHBR and non-UHBR link rates on DP
SST links. This was disabled so far to preserve the fallback behavior.
There isn't a known issue related to such a fallback and DP MST has been
using this for a while already. Also, enabling UHBR rates over
Thunderbolt tunnels in a follow-up change, which at least on some links
supports only 4 lanes and not 1 or 2 lanes on UHBR, makes a
UHBR->non-UHBR fallback scenario more likely.

At the same time align the corresponding link training fallback kunit
test, allowing a UHBR <-> non-UHBR fallback there as well.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.comd>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260714152700.555527-4-imre.deak@intel.com

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This commit is contained in:

Imre Deak 2026-07-14 18:26:57 +03:00

parent eb23a5abd1

commit b03e0f8651

2 changed files with 3 additions and 17 deletions

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5

drivers/gpu/drm/i915/display/intel_dp_link_training.c

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15

drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c

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