clk: imx8mq: Define gates for pll1/2 fixed dividers

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On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate but these gates are not currently defined in
the clock tree.

Add them between sys1/2_pll_out and the fixed dividers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Leonard Crestez 2019-10-16 11:57:37 +00:00 • committed by Shawn Guo

parent 8f2d3c1759

commit b04383b6a5

2 changed files with 62 additions and 21 deletions

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59

drivers/clk/imx/clk-imx8mq.c

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22

include/dt-bindings/clock/imx8mq-clock.h

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